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HA-5190, HA-5195
Data Sheet August 2002 FN2914.4
150MHz, Fast Settling Operational Amplifiers
HA-5190/5195 are operational amplifiers featuring a combination of speed, precision, and bandwidth. Employing monolithic bipolar construction coupled with Dielectric Isolation, these devices are capable of delivering 200V/s slew rate with a settling time of 70ns (0.1%, 5V output step). These truly differential amplifiers are designed to operate at gains 5 without the need for external compensation. Other outstanding HA-5190/5195 features are 150MHz gain bandwidth product and 6.5MHz full power bandwidth. In addition to these dynamic characteristics, these amplifiers also have excellent input characteristics such as 3mV offset voltage and 6.0nV/Hz input voltage noise at 1kHz. With 200V/s slew rate and 70ns settling time, these devices make ideal output amplifiers for accurate, high speed D/A converters or the main components in high speed sample/hold circuits. The 5190/5195 are also ideally suited for a variety of pulse and wideband video amplifiers. Please refer to Application Notes AN525 and AN526 for some of these application designs. At temperatures above 75oC a heat sink is required for the HA-5190 (see Note 2 and Application Note AN556). For military versions, please request the HA-5190/883 data sheet.
Features
* Fast Settling Time (0.1%). . . . . . . . . . . . . . . . . . . . . 70ns * Very High Slew Rate . . . . . . . . . . . . . . . . . . . . . . 200V/s * Wide Gain-Bandwidth (AV 5). . . . . . . . . . . . . . . 150MHz * Full Power Bandwidth . . . . . . . . . . . . . . . . . . . . . 6.5MHz * Low Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 3mV * Input Noise Voltage . . . . . . . . . . . . . . . . . . . . . . 6nV/Hz * Bipolar D.I. Construction
Applications
* Fast, Precise D/A Converters * High Speed Sample-Hold Circuits * Pulse and Video Amplifiers * Wideband Amplifiers
Pinout
HA-5190/95 (CERDIP) TOP VIEW
NC NC
1 2 3 4 5 6 7
14 NC 13 NC 12 NC
Ordering Information
PART NUMBER HA1-5190-2 HA1-5195-5 TEMP. RANGE (oC) -55 to 125 0 to 75 PACKAGE 14 Ld CERDIP 14 Ld CERDIP PKG. NO. F14.3 F14.3
NC -IN +IN VNC
+
11 V+ 10 OUT 9 NC 8 NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002. All Rights Reserved
HA-5190, HA-5195
Absolute Maximum Ratings TA = 25oC
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50mA (Peak)
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) JC (oC/W) CERDIP Package. . . . . . . . . . . . . . . . . . . 75 20 Maximum Junction Temperature (Hermetic Package, Note 1) . .175oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
Temperature Range HA-5190-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC HA-5195-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Heat sinking may be required, especially at TA 75oC. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS Offset Voltage Average Offset Voltage Drift Bias Current Offset Current Input Resistance Input Capacitance Common Mode Range Input Noise Current Input Noise Voltage TRANSFER CHARACTERISTICS
VSUPPLY = 15V, Unless Otherwise Specified TEST CONDITIONS HA-5190-2 TEMP (oC) 25 Full Full 25 Full 25 Full 25 25 Full f = 1kHz, RG = 0 f = 1kHz, RG = 0 25 25 25 Full VCM = 5V VOUT = 90mV, AV = 10 Full 25 25 Full 25 Open Loop 25 25 25 25 25 5V Step to 0.1% 5V Step to 0.01% 2.5V Step to 0.1% 2.5V Step to 0.01% 25 25 25 25 MIN 5 15 5 74 5 5 25 5 160 70 TYP 3 20 5 1 10 1 5 6 30 95 150 8 30 30 6.5 13 8 200 100 50 80 MAX 5 10 15 20 4 6 18 MIN 5 10 5 74 5 150 5 25 5 160 70 HA-5195-5 TYP 3 20 5 1 10 1 5 6 30 95 8 30 30 6.5 13 8 200 100 50 80 MAX 6 10 15 20 4 6 18 UNITS mV mV V/oC A A A A k pF V pA/Hz nV/Hz kV/V kV/V dB V/V MHz V mA MHz ns % V/s ns ns ns ns
Large Signal Voltage Gain (Note 3) Common Mode Rejection Ratio Minimum Stable Gain Gain-Bandwidth-Product OUTPUT CHARACTERISTICS Output Voltage Swing (Note 3) Output Current (Note 3) Output Resistance Full Power Bandwidth (Notes 3, 4) TRANSIENT RESPONSE (Note 5) Rise Time Overshoot Slew Rate Settling Time (Note 5)
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HA-5190, HA-5195
Electrical Specifications
PARAMETER POWER SUPPLY CHARACTERISTICS Supply Current Power Supply Rejection Ratio NOTES: 3. RL = 200, CL < 10pF, VOUT = 5V. Slew Rate 4. Full power bandwidth guaranteed based on slew rate measurement using: FPBW = ---------------------------- . 2V PEAK 5. Refer to Test Circuits section of the data sheet. VS = 10V to 20V Full Full 70 19 90 28 70 19 90 28 mA dB VSUPPLY = 15V, Unless Otherwise Specified (Continued) TEST CONDITIONS HA-5190-2 TEMP (oC) MIN TYP MAX MIN HA-5195-5 TYP MAX UNITS
Test Circuits and Waveforms
IN + OUT 1.6k 200 400
-
NOTES: 6. AV = 5. 7. CL < 10pF.
FIGURE 1. LARGE AND SMALL SIGNAL RESPONSE TEST CIRCUIT
VOUT -5V
+5V 90% 10% VOUT
+1V VIN -1V VIN
Vertical Scale: VIN = 2.0V/Div., VOUT = 4.0/Div. Horizontal Scale: 100ns/Div. LARGE SIGNAL RESPONSE
V+ 0.001F
Vertical Scale: VIN = 50mV/Div., VOUT = 100mV/Div. Horizontal Scale: 100ns/Div SMALL SIGNAL RESPONSE
NOTES:
IN 400
8. AV = -5.
-
1F 0.001F
+
OUT PROBE MONITOR
9. Load Capacitance should be less than 10pF. 10. It is recommended that resistors be carbon composition and that feedback and summing network ratios be matched to 0.1%. 11. Settle Point (Summing Node) capacitance should be less than 10pF. For optimum settling time results, it is recommended that the test circuit be constructed directly onto the device pins. A Tektronix 568 Sampling Oscilloscope with S-3A sampling heads is recommended as a settle point monitor.
1k
V-
1F 2k
SETTLE POINT
5k
FIGURE 2. SETTLING TIME TEST CIRCUIT
3
HA-5190, HA-5195 Schematic Diagram
V+ R1 QP24 QP23 R28 R6 QN22 R7 QP20 QN21 R9 QP19 QP32 D34 D37 D38 D41 QP33 +IN QP36 R26 QP7 QN40 QN43 R10 QN18 R11 QP16 QN17 R12 QP55 R13 QP15 R14 QN13 R15 QN14 QN11 QN12 QN47 QN48 R16 R17 R18 R30 R31 VQN9 QN10 QN45 QN46 QP8 R27 -IN QN1 R24 QN2 C3 R25 D51 D52 R33 QP54 R8 QN56 R2 R3 QP4 QP3 C1 C2 R29 QN49 QN50 QN53 R32 OUT R4 QP6 QP5
QP44
QP35
QN39 QN42
Application Information
Power Supply Decoupling
Although not absolutely necessary, it is recommended that all power supply lines be decoupled with 0.01F ceramic capacitors to ground. Decoupling capacitors should be located as near to the amplifier terminals as possible.
Output Short Circuit
HA-5190/5195 does not have output short circuit protection. Short circuits to ground can be tolerated for approximately 10 seconds. Short circuits to either supply will result in immediate destruction of the device.
Stability Considerations
HA-5190/5195 is stable at gains > 5. Gains < 5 are covered below. Feedback resistors should be of carbon composition located as near to the input terminals as possible.
Heavy Capacitive Loads
When driving heavy capacitive loads (>100pF) a small resistor (100) should be connected in series with the output and inside the feedback loop.
Wiring Considerations
Video pulse circuits should be built on a ground plane. Minimum point to point connections directly to the amplifier terminals should be used. When ground planes cannot be used, good single point grounding techniques should be applied.
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HA-5190, HA-5195 Typical Applications
IN 11pF (NOTE) C1 +
(Also see Application Notes AN525 and AN526)
IN OUT 200 1k (NOTE) +
-
RF 1k (NOTE)
OUT 200
RF 750 (NOTE)
OUTPUT
OUTPUT
INPUT
INPUT
Vertical Scale: 2V/Div. Horizontal Scale: 100ns/Div. NOTE:
Vertical Scale: 2V/Div. Horizontal Scale: 100ns/Div
Values were determined experimentally for optimum speed and settling time. RF and C1 should be optimized for each particular application to ensure best overall frequency response. FIGURE 3. SUGGESTED COMPENSATION FOR NONINVERTING UNITY GAIN AMPLIFIER
1k 1k IN
OUTPUT
+
OUT 200
INPUT
Vertical Scale: 2V/Div. Horizontal Scale: 50ns/Div. FIGURE 4. SUGGESTED COMPENSATION FOR INVERTING UNITY GAIN AMPLIFIER
V+ IN + 200 + 1.6k 120 75 50 1F 1F HA-5033 200 1F 1F 400 V1k 5k 50
-
HA-5190
-
FIGURE 5. VIDEO PULSE AMPLIFIER/75 COAXIAL DRIVER
FIGURE 6. VIDEO PULSE AMPLIFIER COAXIAL LINE DRIVER
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HA-5190, HA-5195 Typical Performance Curves
5
VS = 15V, TA = 25oC, Unless Otherwise Specified
2.0 OPEN LOOP VOLTAGE GAIN (dB) 100 80 60 40 20 0 -20 1K 10K 100K 1M 10M 100M FREQUENCY (Hz) GAIN 0 45 90 135 180 225 PHASE (DEGREES) INPUT NOISE CURRENT (pA/Hz)
INPUT BIAS CURRENT (A)
3
1.2
OFFSET VOLTAGE (mV)
4
BIAS CURRENT
1.6
PHASE
2 OFFSET VOLTAGE 1
0.8
0.4
0 -80
-40
0
40
80
120
0 160
TEMPERATURE (oC)
FIGURE 7. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs TEMPERATURE
FIGURE 8. OPEN LOOP FREQUENCY RESPONSE
18 NORMALIZED PARAMETERS REFERRED TO VALUES AT 25oC OUTPUT VOLTAGE SWING (VP-P) 16 14 12 10 8 6 4 1K
1.2 1.1 1.0 BANDWIDTH 0.9 0.8 0.7 SLEW RATE
10K
100K
1M
10M
100M
-80
-40
0
40
80
120
160
FREQUENCY (Hz)
TEMPERATURE (oC)
FIGURE 9. OUTPUT VOLTAGE SWING vs FREQUENCY
FIGURE 10. NORMALIZED AC PARAMETERS vs TEMPERATURE
1.2 NORMALIZED VALUE REFERRED TO LOAD CAPACITANCE EQUAL TO 10pF
1000 INPUT NOISE VOLTAGE (nV/Hz)
1000
1.1 BANDWIDTH 1.0 SLEW RATE 0.9
100
100
INPUT NOISE CURRENT 10 INPUT NOISE VOLTAGE 10
0.8 10
100 LOAD CAPACITANCE (pF)
200
250
1 1
10
100
1K
10K
1 100K
FREQUENCY (Hz)
FIGURE 11. NORMALIZED AC PARAMETERS vs LOAD CAPACITANCE
FIGURE 12. INPUT NOISE VOLTAGE AND NOISE CURRENT vs FREQUENCY
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HA-5190, HA-5195 Typical Performance Curves
VS = 15V, TA = 25oC, Unless Otherwise Specified (Continued)
OUTPUT VOLTAGE SWING (V)
OUTPUT VOLTAGE STEP (V)
12 10 8 6 4 2
5 5mV 2.5 0 -2.5 5mV -5 0.5mV 0.5mV
0
200
400
600
800
1K
1.2K
0
10
20
30
40
50
60
70
80
90
100
110
LOAD RESISTANCE ()
SETTLING TIME (ns)
FIGURE 13. OUTPUT VOLTAGE SWING vs LOAD RESISTANCE
FIGURE 14. SETTLING TIME FOR VARIOUS OUTPUT STEP VOLTAGES
COMMON MODE REJECTION RATIO (dB)
100 80 60 40 20 0 100
POWER SUPPLY REJECTION RATIO (dB)
120
120 100 80 60 40 20 0 100 NEGATIVE SUPPLY
POSITIVE SUPPLY
1K
10K FREQUENCY (Hz)
100K
1M
1K
10K FREQUENCY (Hz)
100K
1M
FIGURE 15. COMMON MODE REJECTION RATIO vs FREQUENCY
FIGURE 16. POWER SUPPLY REJECTION RATIO vs FREQUENCY
24 VSUPPLY = 15V POWER SUPPLY CURRENT (mA) 20 16 12 8 4 0 -80 VSUPPLY = 10V
-40
0
40
80
120
160
TEMPERATURE (oC)
FIGURE 17. POWER SUPPLY CURRENT vs TEMPERATURE
7
HA-5190, HA-5195 Die Characteristics
DIE DIMENSIONS: 54 mils x 88 mils x 19 mils 1360m x 2240m x 483m METALLIZATION: Type: Al, 1% Cu Thickness: 16kA 2kA PASSIVATION: Type: Nitride (Si3N4) over Silox (SiO2, 5% Phos.) Silox Thickness: 12kA 2kA Nitride Thickness: 3.5kA 1.5kA SUBSTRATE POTENTIAL (Powered Up): VTRANSISTOR COUNT: 49 PROCESS: Bipolar Dielectric Isolation
Metallization Mask Layout
HA-5190
-IN V+
OUTPUT
+IN
V-
8
HA-5190, HA-5195
Ceramic Dual-In-Line Frit Seal Packages (CERDIP)
c1 -A-DBASE METAL E b1 M -Bbbb S BASE PLANE SEATING PLANE S1 b2 b ccc M C A - B S AA C A-B S D Q -CA L DS M (b) SECTION A-A (c) LEAD FINISH
F14.3 MIL-STD-1835 GDIP1-T14 (D-1, CONFIGURATION A) 14 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE
INCHES SYMBOL A b b1 b2 b3 c c1 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.785 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 19.94 7.87 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 90o 14 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 5 6 7 2, 3 8 Rev. 0 4/94
eA
D E e eA eA/2 L Q S1
e
DS
eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 90o 14 0.200 0.060 105o 0.015 0.030 0.010 0.0015
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling dimension: INCH.
aaa bbb ccc M N
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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